Materials Science Forum Vols. 645-648

Abstract: In this paper a wire-bond technology for high temperatures (up to 500°C) based on silver-wire is presented. The mechanical properties of silver thick-wire wedge bonds are analyzed and compared to previously presented silver-stripes fastened onto the chip with the Low Temperature Joining Technique (LTJT) and to common aluminum thick-wire.

Abstract: In this contribution we recapitulate the state of the art of silicon carbide and related materials polishing. Since the demonstration (by Vicente et al) of an ultimate preparation of Si-face -SiC wafers some important progresses were made in the field of surface preparation of silicon carbide and related materials. This concerns the industrial, high output treatments of substrates of increasing size, as well as the research studies of the feasibility of new preparation approaches for wide band gap materials. We also discuss the problems related to the polishing of the polycrystalline material and to the planarization of epilayers.

Abstract: In this study, deep levels are investigated, which are introduced by reactive ion etching (RIE) of n-type/p-type 4H-SiC. The capacitance of as-etched p-type SiC is remarkably small due to compensation or deactivation of acceptors. These acceptors can be recovered to the initial concentration of the as-grown sample after annealing at 1000oC. However, various kinds of defects remain at a total density of ~5× 1014 cm-3 in a surface-near region from 0.3 μm to 1.0 μm even after annealing at 1000oC. The following defects are detected by Deep Level Transient Spectroscopy (DLTS): IN2 (EC – 0.35 eV), EN (EC – 1.6 eV), IP1 (EV + 0.35 eV), IP2 (HS1: EV + 0.39 eV), IP4 (HK0: EV + 0.72 eV), IP5 (EV + 0.75 eV), IP7 (EV + 1.3 eV), and EP (EV + 1.4 eV). These defects generated by RIE can be significantly reduced by thermal oxidation and subsequent annealing at 1400oC.

Abstract: In this paper, we report a new polishing technique regarding the elimination of step bunching on the silicon carbide (SiC) surface. The step bunching generation is often observed as frequent phenomenon on the surface of SiC epilayers grown on low off-angle (0001) SiC wafers and on SiC devices after annealing to activate the dopants. We polished the step bunching surface using a chemical mechanical polishing (CMP) technique reported in a previous study, and we succeeded to improve the morphology with a flat and smooth surface which showed a small Rms value of around 0.1nm. We especially found an excellent polishing effect for the control of leakage current in reverse I-V characteristics of SiC Schottky barrier diodes (SBD).

Abstract: Atomic-force microscopy and scanning tunnel electron microscopy have been used to study the surface of single-crystal 6H-SiC (0001) substrates subjected to step-by-step high-temperature annealing in vacuum. An annealing procedure leading to surface structuring by atomically smooth steps with heights of 0.75 and 1.5 nm has been found. It is suggested to use the structured surfaces as test objects for z-calibration of scanning probe microscopes.

Abstract: Thermal etching of hexagonal (4H-, 6H-, 8H- and 10H-), rhombohedral (15R- and 21R-), and cubic (3C-) SiC Si-faces was performed between 900 and 1000oC in a mixed gas of chlorine (Cl2) and oxygen (O2). In the case of well oriented Si-faces, the 3C-SiC (111) substrate was etched fastest in polytypes. The etching rate in the dislocation-free area depended on the hexagonality. Etch pits with definite shapes appeared, which depend on the type of dislocation and crystal structures. On the basis of these results, etching properties are discussed.

Abstract: Flat and well-ordered surfaces of silicon carbide (SiC) substrates are important for electronic devices. Furthermore, researchers have reported that 4H-SiC surface roughness increases by step-bunching during epitaxial growth and annealing. Degradation of device properties induced by surface roughening is of great concern. Therefore, a method to reduce this surface roughening is requested. We have developed a damage-free planarization method called catalyst-referred etching (CARE). In this paper, we planarized 4H-SiC substrates and evaluated the processed surface before and after the epitaxial growth. Then, we reduced the step-bunching on the epi-wafer surface and determined the electrical properties of the Schottky barrier diodes (SBD) on the processed surface.

Abstract: . 　 Crystallographically specific pyramidal planes in 4H-SiC could be naturally formed at mesa sidewalls by a thermal etching at 900oC in a chlorine (Cl2) based ambience. The mesa structures have been fabricated on the 4H-SiC C-face with 0-45o off-angle toward [11-20]. The etched surface was rather smooth, and bunched step structures on the specific pyramidal planes were not observed with atomic force and scanning electron microscopes. The formation mechanisms of the specific pyramidal planes at mesa sidewalls are discussed on the basis of these experimental results.

Abstract: The impact of CF4 plasma treatment on the surface roughening of SiC has been investigated for N ion implanted SiC(0001) which is implanted with the energy range from 15 to 120 keV at a dose of 9.2 x 1014/cm2. The N ion implanted sample, which is processed by CF4 plasma, shows small surface roughness of 1.6 nm after annealing at 1700 oC for 10 min, while the sample without CF4 plasma treatment shows the large surface roughness (6.6nm) and micro step structure. XPS measurements reveals that CF4 plasma treatment is effective to dissolved the residual oxide on the surface of SiC which is not removed by BHF acid of SiO2 layer on SiC. It is strongly suggested that the formation of micro step structure with the increase of the surface roughness is promoted by the residual oxide such as SiCOx, on SiC.

Abstract: The morphology of a single-crystalline 4H-silicon carbide (SiC) substrate surface after etching by chlorine trifluoride (ClF3) gas was studied over the wide temperature range of 673-1573 K at atmospheric pressure in a horizontal cold wall reactor. The Si-face and C-face showed pitted surfaces at low temperatures; the pits tended to become small and shallow with the increasing substrate temperature. The etching for 0.5 min at the substrate temperature of 1573K and at the ClF3 gas concentration of 1% could maintain a specular surface on both the Si-face and C-face 4H-SiC, the root-mean-square roughness of which was comparable to that of the substrate before etching.