Materials Science Forum Vols. 645-648

Abstract: The nature of the interaction between the substrate and the graphene is critical in terms of impact upon the graphene electron dispersion relation, and in terms of charge transfer. We present here the results of density functional simulations of 4H-SiC–graphene heterostructures using large, periodic simulation supercells. We show that covalent bonding between the substrate and graphene leads both to changes in the electronic structure, and extensive charge transfer, but that the larger simulation system yields qualitatively different electronic structure to that from the more usual p3 × p3R30◦ cell.

Abstract: In this report we review how intrinsic drawbacks of epitaxial graphene on SiC(0001) such as n-doping and strong electronic influence of the substrate can be overcome. Besides surface transfer doping from a strong electron acceptor and transfer of epitaxial graphene from SiC(0001) to SiO2 the most promising route is to generate quasi-free standing epitaxial graphene by means of hydrogen intercalation. The hydrogen moves between the (6p3×6p3)R30◦ reconstructed initial carbon (so-called buffer) layer and the SiC substrate. The topmost Si atoms which for epitaxial graphene are covalently bound to this buffer layer, are now saturated by hydrogen bonds. The buffer layer is turned into a quasi-free standing graphene monolayer, epitaxial monolayer graphene turns into a decoupled bilayer. The intercalation is stable in air and can be reversed by annealing to around 900 °C. This technique offers significant advances in epitaxial graphene based nanoelectronics.

Abstract: We report on a comprehensive study of the properties of quasi-freestanding monolayer and bilayer graphene produced by conversion of the (6√3×6√3)R30° reconstruction into graphene via intercalation of hydrogen. The conversion is confirmed by photoelectron spectroscopy and Raman spectroscopy. By using infrared absorption spectroscopy we show that the underlying SiC(0001) surface is terminated by hydrogen in the form of Si-H bonds. Using Hall effect measurements we have determined the carrier concentration and type as well as the mobility which lies well above 1000 cm2/Vs despite a significant amount of short range scatterers detected by Raman spectroscopy.

Abstract: Epitaxial graphene (EG) grown on the carbon-face of SiC has been shown to exhibit high carrier mobilities, in comparison to other growth techniques amenable to wafer-scale graphene fabrication. The transfer of large area (>mm2) graphene films to substrates amenable for specific applications is desirable. We demonstrate the dry transfer of EG from the C-face of 4H-SiC onto SiO2, GaN and Al2O3 substrates via two approaches using either 1) thermal release tape or 2) a spin-on, chemically-etchable dielectric. We will report on the impact that these transfer processes has upon the electrical properties of the transferred EG films.

Abstract: We report on electrical measurements on epitaxial graphene on 6H-SiC (0001). The graphene layers were fabricated by thermal decomposition in Argon atmosphere. Large van der Pauw structures and Hall bars were patterned by e-beam lithography, the Hall bars ranged from rather large structures down to sub-micrometer sized Hall bars entirely placed on atomically °at substrate terraces. We present Hall measurements in a broad temperature range, Shubnikov de Haas oscillations and quantum Hall steps. The data lead to the conclusion that electrons in epitaxial graphene have the same quasi-relativistic properties previously shown in exfoliated graphene. A remarkable di®erence, however, is the stronger coupling to substrate phonons and the relatively high charging being an intrinsic property of this epitaxial system.

Abstract: Extended defects and deep levels generated during epitaxial growth of 4H-SiC and device processing have been reviewed. Three types in-grown stacking faults, (6,2), (5,3), and (4,4) structures, have been identified in epilayers with a density of 1-10 cm-2. Almost all the major deep levels present in as-grown epilayers have been eliminated (< 1x1011 cm-3) by two-step annealing, thermal oxidation at 1150-1300oC followed by Ar annealing at 1550oC. The proposed two-step annealing is also effective in reducing various deep levels generated by ion implantation and dry etching. The interface properties and MOSFET characteristics with several gate oxides are presented. By utilizing the deposited SiO2 annealed in N2O at 1300oC, a lowest interface state density and a reasonably high channel mobility for both n- and p-channel MOSFETs with an improved oxide reliability have been attained.

Abstract: The authors have investigated effects of thermal oxidation on deep levels in the whole energy range of bandgap of 4H-SiC which are generated by ion implantation, by deep level transient spectroscopy (DLTS). The dominant defects in n-type samples after ion implantation and high-temperature annealing at 1700oC, IN3 (Z1/2: Ec – 0.63 eV) and IN9 (EH6/7: Ec – 1.5 eV) in low-dose-implanted samples, can be remarkably reduced by oxidation at 1150oC. However, in p-type samples, the IP8 (HK4: Ev + 1.4 eV) survives and additional defects, several defects such as IP4 (HK0: Ev + 0.72 eV) appear after thermal oxidation in low-dose-implanted samples. The defects except for the IP8 center can be reduced by subsequent annealing at 1400oC. These phenomena are explained by a model that excess interstitials are generated at the oxidizing interface and diffuse into the bulk region.

Abstract: The influences of processing and material defects on the electrical characteristics of large-capacity (approximately 100A) SiC-SBDs and SiC-MOSFETs have been investigated. In the case of processing defects, controlled activation annealing is the most important factor. On the other hand for material defects, the number of epitaxial defects must be decreased to zero for both SBDs and MOSFETs. The dislocation defects in SiC wafers are dangerous for the breakdown voltage of MOSFETs. However, they are not killer defects. If the epitaxial defect density is sufficiently low and the dislocation density is in the order of 10000cm-2, the long- term reliability of the gate oxide at the electric field of 3MV/cm can be guaranteed.

Abstract: In this work, the electrical performance in terms of maximum current gain, ON-resistance and blocking capability has been compared for 4H-SiC BJTs passivated with different surface passivation layers. Variation in BJT performance has been correlated to densities of interface traps and fixed oxide charge, as evaluated through MOS capacitors. Six different methods were used to fabricate SiO2 surface passivation on BJT samples from the same wafer. The highest current gain was obtained for PECVD deposited SiO2 which was annealed in N2O ambient at 1100 °C during 3 hours. Variations in breakdown voltage for different surface passivations were also found, and this is attributed to differences in fixed oxide charge that can affect the optimum dose of the high voltage JTE termination.

Abstract: In this work we discuss a structure of a p-doped Poly-Si layer and a Ni layer deposited onto n-type 4H-SiC in order to form a Schottky-like contact which undergoes a specific temperature budget to establish a temperature independent forward characteristic of the formed rectifying junction. The results of our treatment is discussed in terms of a hetero junction, though temperature treated NiSi-layers normally are expected to show an ohmic behavior.