Materials Science Forum Vols. 645-648

Abstract: We discuss the influence of negative charging on high-rate ICP etching of SiC via-holes for GaN HEMT MMICs. There is large differential etching behavior such as etch rate, etching profile, and RIE lag between S.I.- and n-SiC substrates because of the difference in wafer heating and negative charging of the sidewall during etching between both substrates. We analyze the difference in negative charging between both substrates by simulating the etching profile.

Abstract: We have developed a novel planarization technique for gallium nitride (GaN) substrates using a photo-electro chemical process and solid acid catalyst. In this method, a GaN surface is oxidized by ultraviolet (UV) light irradiation, and the oxide layer is chemically removed by a solid acid catalyst. In the current work, the dependence of the removal rate on the UV light intensity was investigated.

Abstract: This paper discusses the issues regarding reliability of large-area (up to 25mm2) gate oxide on the C-face of 4H-SiC. We have shown that the TDDB characteristics of large-area gate oxide improved by separating gate oxidation processes into oxide growth by dry-oxidation and successive interface control by anneal in N2O ambient or that by wet-oxidation followed by anneal in H2 ambient. In particular, dry-oxidation followed by anneal in N2O ambient for interface treatment (dry+N2O process) is effective for the suppression of the random failure in TDDB characteristics. The estimated lifetime of gate oxide of less than 9mm2 by the dry+N2O process is six-digits larger than 30 years. In the case of the TDDB characteristics of 25mm2 gate oxide grown by the dry+N2O process, the initial and random failure in TDDB characteristics is dominant. However, even in this case, we have confirmed that the evaluated lifetime of 25mm2 gate oxide is more than 30 years. In order to clarify the mechanism of the degradation of the TDDB characteristics of large-area gate oxide, we examined the effect of the surface defect on the TDDB characteristics by observing the surface of each broken MOS capacitor after the TDDB test. We have found following results. (1) The initial failures in TDDB characteristics are mainly due to surface defects such as “down fall”, “comet”, and “triangular defect”. (2) The footprints of random failure do not correspond to the positions of smaller surface defects such as “bump”. Finally, we have found that the quality of the epitaxial layer affects random failure rate in the TDDB characteristics of large area gate oxide; the random failure in the TDDB characteristics of 25mm2 gate oxide on epitaxial layer grown by a certain epitaxial vendor is almost suppressed. However, the cause of the difference in TDDB characteristics is not identified.

Abstract: Reliability of the gate oxide on SiC is a pressing concern for deploying SiC MOS-based devices in real systems. While good projected oxide reliability was obtained recently under highly accelerated test conditions, indication that such projection may not be valid at lower operating fields was also reported. In this work, results from long-term TDDB stress (over 7 months) at 6 MV/cm and 300 °C on 4H-SiC MOS capacitors is reported. We confirm that lifetime projection from high-field data continues to be valid and no change in field acceleration factor is observed. The discrepancy between our results and the early prediction of poor reliability is examined.

Abstract: We have tried to apply the oxidation model of SiC proposed previously, termed ‘Si-C emission model’, to the oxide growth rate at various oxidation temperatures. We have found that the model well reproduces the oxide thickness dependences of oxide growth rates for all of the temperatures measured for both of the SiC Si- and C-faces. We have estimated the temperature dependence of oxide depth profiles of Si and C interstitials by using the Si-C emission model, and discussed the structure at/near the SiC–oxide interface.

Abstract: We have investigated the oxidation process of SiC (000-1) C-face at low oxygen partial pressures using an in-situ spectroscopic ellipsometry. The oxide growth rate decreased steeply at the early stage of oxidation and then slowly decreased with increasing oxide thickness. The initial oxide growth rate was almost proportional to the oxygen　partial　pressure for both the polar directions. This result suggests that the initial interfacial reaction rate is constant regardless of the concentration of oxidants reaching the interface.

Abstract: Rapid Thermal Processing (RTP) has been evaluated as an alternative to conventional furnace technique for oxidation of 4H- and 3C-SiC. We show that the growth of the SiO2 films in a RTP chamber is orders of magnitude faster than in a conventional furnace. As well as being fast, this process leads to oxide films with quality comparable or even better than the one grown in classical furnaces. Studying different gas for oxidizing and annealing ambient, we demonstrate that SiO2/SiC interface is significantly improved when using N2O instead of O2 or even N2-O2 dilution.

Abstract: The dielectric breakdown mechanism in 4H-SiC metal-oxide-semiconductor (MOS) devices was studied using conductive atomic force microscopy (C-AFM). We performed time-dependent dielectric breakdown (TDDB) measurements using a line scan mode of C-AFM, which can characterize nanoscale degradation of dielectrics. It was found that the Weibull slope () of time-to-breakdown (tBD) statistics in 7-nm-thick thermal oxides on SiC substrates was much larger for the C-AFM line scan than for the common constant voltage stress TDDB tests on MOS capacitors, suggesting the presence of some weak spots in the oxides. Superposition of simultaneously obtained C-AFM topographic and current map images of SiO2/SiC structure clearly demonstrated that most of breakdown spots were located at step bunching. These results indicate that preferential breakdown at step bunching due to local electric field concentration is the probable cause of poor gate oxide reliability of 4H-SiC MOS devices.

Abstract: In this paper, nitrided insulators such as N2O-grown oxides, deposited SiO2 annealed in N2O, and deposited SiNx/SiO2 annealed in N2O on thin-thermal oxides have been investigated for realization of high performance n- and p-type 4H-SiC MIS devices. The MIS capacitors were utilized to evaluate MIS interface characteristics and the insulator reliability. The channel mobility was determined by using the characteristics of planar MISFETs. Although the N2O-grown oxides are superior to the dry O2-grown oxides, the deposited SiO2 and the deposited SiNx/SiO2 exhibited lower interface state density (n-MIS: below 7x1011 cm-2eV-1 at EC-0.2 eV, p-MIS: below 6x1011 cm-2eV-1 at EV+0.2 eV) and higher channel mobility (n-MIS: over 25 cm2/Vs, p-MIS: over 10 cm2/Vs). In terms of reliability, the deposited SiO2 annealed in N2O exhibits a high charge-to-breakdown over 50 C/cm2 at room temperature and 15 C/cm2 at 200°C. The nitrided-gate insulators formed by deposition method have superior characteristics than the thermal oxides grown in N2O.

Abstract: The electrical properties of oxides fabricated on n-type 3C-SiC (001) using wet oxidation and an advanced oxidation process combining SiO2 deposition with rapid post oxidation steps have been compared. Two alternative SiO2 deposition techniques have been studied: the plasma enhanced chemical vapor deposition (PECVD) and the low pressure chemical vapor deposition (LPCVD). The post-oxidized PECVD oxide is been demonstrated to be beneficial in terms of interface traps density and reliability.