Materials Science Forum Vols. 645-648

Abstract: This paper presents a study on a SiC JFET leg of a 3-leg Voltage Source Inverter (VSI). The switching curves obtained with the JFET working in free wheeling mode are shown to point out drain-to-gate interaction effects. Indeed, during the drain-source voltage variations, the JFET gate-source voltage can have considerable variations, because of the electrical coupling induced by the gate-drain capacitance Cgd. When the gate-source voltage variation becomes too negative, there is a risk of occurrence of the phenomenon of punch-through in the gate-source junction. Conversely, when it is enough positive, the JFET may conduct and lead to a leg short-circuit. To decrease these undesired effects for the JFET legs and consequently for the SiC JFET inverter, an external gate-source capacitor is used. This solution is studied and optimized by simulation on an inverter leg.

Abstract: The 1.2 kV 4H-SiC buried-grid vertical JFET structures with Normally-on (N-on) and Normally-off (N-off) design were investigated by simulations. The conduction and switching properties were determined in the temperature range from -50°C to 250°C. In this paper, the characteristics of the N-on designs with threshold voltage (Vth) of -50 V and -10 V are compared with the N-off design (Vth=0). The presented data are for devices with the same channel length at 250°C. The results show that the on-resistance (Ron) decreases with increasing channel doping concentration and decreasing channel width. The presented turn-on, Eon, and turn-off, Eoff, energies per pulse are calculated under the switching conditions 100 A/cm2 and 600 V with a gate resistance of Rg=1
. For the two N-on designs the total switching losses, Esw=Eon+Eoff, differ less than 30% with Wch  0.7 m. With Wch=0.5 m the switching losses of N-off design are almost one order of magnitude higher than those of the N-on design with Vth = -50 V.

Abstract: The main problem when the conventional PSpice JFET model is used to simulate a vertical short-channel buried-grid JFET is caused by the constant values of Threshold Voltage (VTO) and Transconductance (BETA). This paper presents a new model for the vertical short-channel buried-grid 1200V JFET, where both VTO and BETA vary with respect to the Drain-Source voltage. Simulation data from Medici have been analyzed in order to extract the analytical equations for VTO and BETA. Also other PSpice parameters are extracted from these data. The proposed circuit model has been simulated in Matlab by optimizing the same algorithm that PSpice uses. A variety of results are shown and discussed in this paper.

Abstract: In this paper, we review the performance, reliability, and robustness of the current 4H-SiC power DMOSFETs. Due to advances in device and materials technology, high power, large area 4H-SiC power DMOSFETs (1200 V, 67 A and 3000 V, 30 A) can be fabricated with reasonable yields. The availability of large area devices has enabled the demonstration of the first MW class, all SiC power modules. Evaluations of 1200 V 4H-SiC DMOSFETs showed that the devices offer avalanche power exceeding those of commercially available silicon power MOSFETs, and have the sufficient short circuit robustness required in most motor drive applications. A recent TDDB study showed that the gate oxides in 4H-SiC MOSFETs have good reliability, with a 100-year lifetime at 375oC if Eox is limited to 3.9 MV/cm. Future work on MOS reliability should be focused on Vth shifts, instead of catastrophic failures of gate oxides.

Abstract: We present physics based models for the occupation of interface traps and the mobility of the transition layer found in 4H-SiC MOSFETs and extract values for the same using combined numerical simulation and experimental characterization. The Si-C-O transition layer found in 4H-SiC MOS devices is electrically modeled as having a doping dependent mobility that is different from the regular bulk 4H-SiC bulk mobility. Compared to the high intrinsic bulk mobility of 4H-SiC, the transition layer intrinsic mobility was extracted to be approximately 165cm2/Vs. The occurrence of the excessive high density of interface traps near the conduction band edge led us to develop a new model for the occupation of traps lying inside the conduction band itself. Due to the conduction band trap densities being comparable to the conduction band electron states, a non-zero probability exists for their occupation, which causes the occupied trap densities to be very high in strong inversion. Detailed numerical simulations and corroboration with experiment have been performed to calibrate the models and extract physical parameter values.

Abstract: Low channel mobility is one of the biggest challenges to commercializing SiC MOSFETs. Accurate mobility measurement is essential for understanding the mechanisms that lead to low mobility. The most widely used effective mobility measurements overestimate the inversion charge for devices that have high level of defects. Mobility measured by the Hall effect is more accurate; however the conventional Hall mobility measurement is tedious. In this work, we demonstrate a wafer-level Hall measurement technique, which is simple and convenient to implement. With this method, extensive study of the mobility degradation is possible.

Abstract: We have observed a noticeable increase in the instability of the I-V characteristics following an ON-state current stress, especially in the subthreshold region. An increased stretch-out and negative shift can give rise to increased leakage current in the OFF-state if proper precautions are not met to provide a proper margin for the threshold voltage. State-of-the-art 50-A MOSFETs exhibit less instability than previous 20-A devices, and devices that run hotter show a larger degradation.

Abstract: Silicon carbide Double-Implanted Metal-Oxide-Semiconductor Field-Effect Transistors (DIMOSFETs) were fabricated on 4H-SiC (000-1) carbon face. The DIMOSFETs were characterized from room temperature to 250°C. At room temperature, they showed a specific on-resistance of 4.9 mΩcm2 at a gate bias of 20 V and a drain voltage of 1.0 V. The specific on-resistance taken at a drain current (Id) of 260 A/cm2 was 5.0 mΩcm2. The blocking voltage of this device was higher than 1360 V at room temperature. At 250°C, the specific on-resistance increased from 5.0 mΩcm2 to 12.5 mΩcm2 and the threshold voltage determined at Id = 26 mA/cm2 decreased from 5.5 V to 4.3 V.

Abstract: We investigated the impact of a combination treatment of nitrogen plasma exposure and forming gas annealing (FGA) for a thermally grown SiO2 layer on channel electron mobility in 4H-SiC metal-insulator-semiconductor field-effect-transistors (MISFETs) with and without deposited aluminum oxynitride (AlON) overlayers. This treatment was effective for improving the interface properties of nitrided SiO2/SiC structures formed by thermal oxidation in NOx ambient as well as pure SiO2/SiC structures. A channel mobility enhancement was perfectly consistent with a reduction in interface state density depending on the process conditions of the combination treatment, and a peak mobility of 26.9 cm2/Vs was achieved for the MISFETs with the nitrided SiO2 single dielectric layer. Comparable channel mobility was obtained with a gate insulator consisting of the AlON stacked on a thin nitrided SiO2 interlayer, indicating that both the combination treatment and the AlON/SiO2 stacked dielectrics can be integrated into the SiC MISFET fabrication processes.

Abstract: We fabricated 4H-silicon carbide (SiC) Complementary Metal-Oxide-Semiconductor (CMOS) devices with wet gate oxidation processing. The channel properties of n-channel MOS Field-Effect-Transistor (NMOS) were controlled by buried channel (BC) structure. The electrical properties of CMOS devices depended on the doping concentration of the BC-layer (Nbc) for NMOS. The SiC CMOS inverters with high Nbc indicated fast operation at the delay time (Td) of 4.8 ns for supply voltage of 15 V. To our knowledge, Td obtained in this study is the smallest among the reported values for SiC CMOS inverters.