Silicon Carbide and Related Materials 2009

Volumes 645-648

doi: 10.4028/

Paper Title Page

Authors: Shinsuke Harada, Sachiko Ito, Makoto Kato, Akio Takatsuka, Kazutoshi Kojima, Kenji Fukuda, Hajime Okumura
Abstract: UMOSFET is theoretically suitable to decrease the on-resistance of the MOSFET. In this study, in order to determine the cell structure of the SiC UMOSFET with extremely low on-resistance, influences of the orientation of the trench and the off-angle of the wafer on the MOS properties are investigated. The channel resistance, gate I-V curves and instability of threshold voltage are superior on the {11-20} planes as compared with other planes. On the vicinal off wafer, influence of the off-angle disappears and the properties on the equivalent planes are almost the same. The obtained results indicate that the extremely low on-resistance with the high stability and high reliability is possible in the SiC UMOSFET by the hexagonal cell composed of the six {11-20} planes on the vicinal off wafer, and actually an extremely low channel resistance was demonstrated on the hexagonal UMOSFET with the six {11-20} planes on the vicinal off wafer.
Authors: Vinayak Tilak, Kevin Matocha, Greg Dunne
Abstract: nversion layers of 4H and 6H Silicon carbide based MOS devices are characterized by Gated Hall measurements to determine the trap density close to the conduction band edge and the main scattering mechanisms that limit the mobility. MOS gated Hall structures were fabricated on 4H SiC polytype with p-type doping of 5X1015cm-3 and 2X1017cm-3. MOS Gated Hall structures were also fabricated on 6H SiC polytype with p-type doping of 7.5X1015cm-3. The gate oxide was grown thermally with N2O as a precursor followed by a NO post oxidation anneal. The inversion layer Hall mobility on the 6H SiC MOSFET sample decreased with increasing temperature from room temperature to 423K, while on the 4H SiC MOSFET samples the inversion layer mobility increased slowly. Approximately 50% of the total charge density at the interface of both 6H and 4H SiC MOSFETs was found to be trapped charge. The dominant scattering mechanism in 6H SiC MOSFETs was inferred to be phonon scattering based on the temperature dependence and theoretical estimates of the phonon limited mobility. In the case of 4H SiC, we infer that at surface roughness scattering is the dominant scattering mechanisms at high surface fields.
Authors: Takafumi Tanehira, T. Nakano, Motoi Nakao
Abstract: Metal oxide semiconductor field effect transistors (MOSFETs) using SiC on insulator (SiC-OI) substrate with the structure of 3C-SiC (100)/SiO2/Si have been fabricated. SiC-OI substrates with SiC thicknesses of 100 nm and 600 nm are employed as starting materials and aluminum ions are implanted for p-regions or channel regions with a multi-implantation technique. Afterward, to form the source and drain regions, phosphorus ions are implanted. The gate oxide layer is grown in dry thermal oxidation, followed by post-oxidation annealing. Nickel is used as a contact material for the source and drain region, and aluminum is used for the gate material. From Id-Vd characteristics, 600 nm SiC-OI MOSFET is superior to 100 nm SiC-OI MOSFET. It is might that the crystalline quality of surface SiC layers affects the performance of MOSFET. SiC-OI MOSFET is operated successfully for the first time.
Authors: Kin Kiong Lee, Jamie Steward Laird, Takeshi Ohshima, Shinobu Onoda, Toshio Hirao, Hisayoshi Itoh
Abstract: This paper investigates the transient induced currents by energetic carbon ions in 6H-SiC MOSFETs and the carrier dynamic response due to such a heavy ion collision is simulated by Technology Computer Aided Design (TCAD). It was found that a heavy ion strike induces a bipolar effect on the transistor, whereby the current transients can vary in both polarities. And this has been attributed to the inherent in the MOSFET is a parasitic bipolar junction transistor.
Authors: Anant K. Agarwal, Qing Chun Jon Zhang, Robert Callanan, Craig Capell, Albert A. Burk, Michael J. O'Loughlin, John W. Palmour, Victor Temple, Robert E. Stahlbush, Joshua D. Caldwell, Heather O'Brian, Charles Scozzie
Abstract: In this paper, for the first time, we report a large area (1 cm2) SiC GTO with 9 kV blocking voltage fabricated on 100-mm 4H-SiC substrates with much reduced Basal Plane Dislocation (BPD) density. The static and dynamic characteristics are described. A forward drop of 3.7 V at 100 A (100 A/cm2) is measured at 25°C. A slight positive temperature coefficient of the forward drop is present at 300 A/cm2, indicating the possibility of paralleling multiple devices for higher current capability. The device exhibits extremely low leakage currents at high temperatures. The device has shown fast turn-on time of 53.9 nsec, and ~3.5 s of turn-off time, respectively. A stable forward voltage drop after electrical stress for >1000 hours has been achieved.
Authors: Siddarth G. Sundaresan, H. Issa, Deepak Veeredy, Ranbir Singh
Abstract: This study is focused on the design and fabrication of large-area (4.1x4.1 mm2 and 8.2x8.2 mm2), 8.1 kV 4H-SiC GTO Thyristors. The anode and gate fingers of Thyristors were designed with involute, cellular or hexagonal patterns. Forward blocking voltages as high as 8106 V and On-state voltage drop (Von) and differential specific on-resistance (Ron,sp) as low as 3.8 V and 6 mΩ-cm2 at 100 A/cm2 were measured on these devices. About 59% of 4.1 x4.1 mm2 and 29% of 8.2x8.2 mm2 Thyristors blocked voltages in excess of 6 kV. Detailed investigations revealed the impact of different anode/gate finger geometries on the device characteristics. Preliminary pulsed power characterization of the GTO Thyristors was also performed.
Authors: Qing Chun Jon Zhang, Robert Callanan, Anant K. Agarwal, Albert A. Burk, Michael J. O'Loughlin, John W. Palmour, Charles Scozzie
Abstract: 4H-SiC Bipolar Junction Transistors (BJTs) and hybrid Darlington Transistors with 10 kV/10 A capability have been demonstrated for the first time. The SiC BJT (chip size: 0.75 cm2 with an active area of 0.336 cm2) conducts a collector current of 10 A (~ 30 A/cm2) with a forward voltage drop of 4.0 V (forced current gain βforced: 20) corresponding to a specific on-resistance of ~ 130 mΩ•cm2 at 25°C. The DC current gain, β, at a collector voltage of 15 V is measured to be 28 at a base current of 1 A. Both open emitter breakdown voltage (BVCBO) and open base breakdown voltage (BVCEO) of ~10 kV have been achieved. The 10 kV SiC Darlington transistor pair consists of a 10 A SiC BJT as the output device and a 1 A SiC BJT as the driver. The forward voltage drop of 4.5 V is measured at 10 A of collector current. The DC forced current gain at the collector voltage of 5.0 V was measured to be 440 at room temperature.
Authors: Hiroki Miyake, Tsunenobu Kimoto, Jun Suda
Abstract: In this study, new SiC-based heterojunction bipolar transistors (HBT) are proposed. An n-type AlN/GaN short-period superlattice (quasi-AlGaN) layer is grown on a SiC pn junction as a widegap emitter. By using quasi-AlGaN emitter, we have demonstrated successful control of band offset of AlGaN/SiC. Quasi-AlGaN/SiC HBT with an Al content over 0.5, which has no potential barrier to electron injection from an n-AlGaN emitter to a p-SiC base, exhibited a common-emitter current gain of β ~ 2.7, whereas the HBT with an Al content below 0.5 showed β ~ 0.1.
Authors: Martin Domeij, Carina Zaring, Andrei O. Konstantinov, Muhammad Nawaz, Jan Olov Svedberg, Krister Gumaelius, Imre Keri, Anders Lindgren, Bo Hammarlund, Mikael Östling, Mats Reimark
Abstract: This paper reports large active area (15 mm2) 4H-SiC BJTs with a low VCESAT=0.6 V at IC=20 A (JC=133 A/cm2) and an open-base breakdown voltage BVCEO=2.3 kV at T=25 °C. The corresponding room temperature specific on-resistance RSP-ON=4.5 mΩcm2 is to the authors knowledge the lowest reported value for a large area SiC BJT blocking more than 2 kV. The on-state and blocking characteristics were analyzed by device simulation and found to be in good agreement with measurements. Fast switching with VCE rise- and fall-times in the range of 20-30 ns was demonstrated for a 6 A 1200 V rated SiC BJT. It was concluded that high dynamic base currents are essential for fast switching to charge the BJT parasitic base-collector capacitance. In addition, 10 μs short-circuit capability with VCE=800 V was shown for the 1200 V BJT.
Authors: Luca Farese, Bengt Gunnar Malm, Martin Domeij, Mikael Östling
Abstract: SiC power bipolar junction transistors (BJTs), for high voltage applications, have been studied under elevated temperature and electrical stress conditions. Electroluminescence has been used to capture effects of defect motion and growth, in complete transistor structures, leading to a quantifiable degradation in the electrical performance. The observed degradation of current gain (β) and on-resistance (RON) was relatively modest and saturated after a limited stress time, resulting in stable device performance. The characteristic wavelength (450 nm) of the electroluminescence, or light emission, in the visual and near infrared (NIR) range, coupled to the shape of the defects indicates that basal plane dislocations and stacking faults are involved.

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