Materials Science Forum Vols. 645-648

Abstract: This research is focused on the influence of high C/Si ratios and low pressure on n-type doping concentration and surface defects of 4H-SiC C-face epilayers. N-type doping concentration decreases as C/Si ratio increases from 3.0 to 4.0 and pressure reduces from 100 mbar to 50 mbar; defect densities decrease as pressure increases at both C/Si ratios of 3.0 and 4.0. RMS roughness is about 0.21 nm for all C-face samples, independent of C/Si ratios of 3.0 and 4.0 and pressure from 50 mbar to 100 mbar. However, the influence of growth temperature on doping concentration and surface defects can not be clearly observed in this work.

Abstract: Starting from 3C-SiC(111) layers grown by Vapour-Liquid-Solid mechanism, homoepitaxial growth by Chemical Vapour Deposition was carried out on top of these seeds. The effect of the growth temperature and of the C/Si ratio in the gas phase was investigated on the surface morphology, the roughness and the defect density. It was found that the initial highly step-bunched surface of the VLS seeds could be greatly smoothen using appropriate conditions. These conditions were also found to reduce significantly the defect size and/or density at the surface.

Abstract: Thin films of SiC have been deposited using a hollow cathode sputtering technique. Several methods have been used including DC, RF, and pulsed sputtering. The films reported here have been deposited using DC and pulsed sputtering.

Abstract: 3C-SiC devices are hampered by the defect density in heteroepitaxial films. Acting on the substrate, it is possible to achieve a better compliance between Si and 3C-SiC. We present here an approach to favorite defect geometrical reduction in both [ ] and [ ] directions by creating Inverted Silicon Pyramids (ISP). A study of 3C-SiC growth on ISP is reported showing benefits in the film quality and a reduction in the linear density of stacking faults. Growth on ISP leads also to a decrease in the 3C-SiC residual stress as well as in the bow of the Si/SiC system.

Abstract: 3C-SiC films were grown on Si by VPE using CBr4 as the carbon source, at temperatures ranging between 1100 to 1250°C. XRD, TEM, AFM, and SEM results indicate that the epitaxy proceeds as a 3D growth of uncoalesced islands at low temperature, whereas a continuous layer with hillocks on top is obtained above 1200°C. The shape and faceting of the islands are analyzed by AFM, showing (311) preferred facets.

Abstract: SiC is a candidate material for micro- and nano-electromechanical systems (MEMS and NEMS). In order to understand the impact that the growth rate has on the residual stress of CVD-grown 3C-SiC hetero-epitaxial films on Si substrates, growth experiments were performed and the resulting stress was evaluated. Film growth was performed using a two-step growth process with propane and silane as the C and Si precursors in hydrogen carrier gas. The film thickness was held constant at ~2.5 µm independent of the growth rate so as to allow for direct films comparison as a function of the growth rate. Supported by profilometry, Raman and XRD analysis, this study shows that the growth rate is a fundamental parameter for low-defect and low-stress hetero-epitaxial growth process of 3C-SiC on Si substrates. XRD (rocking curve analysis) and Raman spectroscopy show that the crystal quality of the films increases with decreasing growth rate. From curvature measurements, the average residual stress within the layer using the modified Stoney’s equation was calculated. The results show that the films are under compressive stress and the calculated residual stress also increases with growth rate, from -0.78 GPa to -1.11 GPa for 3C-SiC films grown at 2.45 and 4 µm/h, respectively.

Abstract: Temperature dependence of the growth rate of 3C-SiC(001) films on Si(001) substrates during ultralow-pressure (ULP: ~10-1 Pa) CVD using monomethylsilane has been investigated in detail by using pyrometric interferometry. A novel behavior, i.e. a sharp division of the growth mode into two regimes depending on the growth temperature, has been found to exist. Based on this finding, we have developed a two-step process, which realizes a low-temperature (900 °C), high-rate growth of single-crystalline 3C-SiC film on Si substrates, whose rate of 3 m/h is extremely high for this ULP process.

Abstract: Usually a waiting step at around 1000°C to 1100°C during the carbonization step for 3C-SiC on silicon is implemented for establishing a closed carbon layer to prevent the formation of voids. The latter, however, may lead to non-ideal nucleation conditions for high quality layers with a low density of domain boundaries. Our investigations indicate that a continuous ramp-up as fast as possible with no waiting step would be preferable. The worst layer quality, as measured by peak intensity and FWHM of the (200) reflection of 3C SiC, can be found at a temperature of about 1000°C, which indicates that here the nucleation rate would be the highest. So longer periods within this temperature range should be avoided by applying high ramping speeds during the carbonization step.

Abstract: We investigate by means of Atomic Force Microscopy and Scanning Electron Microscopy the surface modifications of 3C-SiC(111)/Si epilayers induced by thermal annealing performed under hydrogen or argon atmosphere. We explore the effects of these treatments both on as grown and polished epilayers. Owing to an important initial surface roughness, the annealing has few impact on as grown films. On polished epilayers, a surface reorganization via the formation of a regular array of steps is evidenced. The proper effect of each gas on the surface reorganization is discussed.

Abstract: Germanium modified silicon surfaces in combination with two step epitaxial growth technique consisting in conversion of the Si(100) substrate near surface region into 3C-SiC(100) followed by an epitaxial growth step allows the manipulation of the residual strain. The morphology and the residual strain in dependence on the Ge coverage are only affected by the Ge quantity and not by the growth technique. The positive effect of the Ge coverage is attributed to changes in the morphology during the conversion process, as well as to a reduced lattice and thermal mismatch between SiC and Si in consequence of alloying the near surface region of the Si substrate with Ge.